A LOW POWER SRAM CELL DESIGN WITH BIT-INTERLEAVING CAPABILITY IN DSM TECHNOLOGY

Abstract

SRAM cell is the basic memory devices which is made from the combination of Flip Flop and registers for storage of data. In this paper we have proposed a novel design which exhibits lower power consumption and better stability as compared to the other existing designs when scaling of technology takes place. This proposed 11T SRAM has been compared with standard 6T SRAM, 7T SRAM cell, 8T SRAM Cell and 9T SRAM (with bit-interleaving capability) in term of Power consumption, Delay and Power Delay Product (PDP) at various supply voltages as 1.8V, 1.6V and 1.4V. For the stability analysis SNM (Static Noise Margin) also analyzed at the supply voltage 1.8V. The simulations are carried out on Cadence Virtuoso at 180nm CMOS technology and the simulation results are analyzed to verify the superiority of the proposed design over the existing designs. The higher noise margin confirms the high speed of the SRAM cell. In this paper, the proposed 11T SRAM cell shows maximum reduction in power consumption of 24.17% with 6T, of 88.6% with 7T, of 28.21% with 8T and of 35.03% with 9T, maximum reduction in delay of 9.1% with 6T, of 64.26% with 7T, of 9.18% with 8T and of 10.44% with 9T and maximum SNM of 35.02% with 6T, of 32.27% with 7T, of 34.4% with 8T and of 33.15% with 9T increases