IMPLEMENTATION OF MCC ADDER WITH LOW POWER DISSIPATION BASED ON SPST - Vidhya.M, Kamalakannan.R.S (International Journal of Research Science and Management, 2015)
This paper presents the implementation of an 8-bit Manchester carry chain (MCC) adder and design exploration and applications of a low-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multi output domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module. These two design examples have quite different hardware configurations, thus, the realization issues of the SPST on every design also remarkably differ from each other.